![]() In a 3-to-8 decoder, three inputs are decoded into eight outputs. This type of decoders is available in IC forms so that 3 to 8, 4 to 16, and 5 to 32 decoders can also be made depends on the application requirement. Therefore, only one output will be low for any combinations of inputs at a given time and all other outputs will be high. If both inputs are zero (A = B = 0), Y0 will be zero, if A = 0 and B= 1, then Y1 will be 1 and so on. To generate the minterms, we have to use NAND gates which act as inverters. This is constructed with a principle of max terms as outputs. It is also possible to design 2-to-4 decoder using NAND gates as shown in figure below along with truth table. Each output represents one of the minterms of the 2 input variables. Two NOT gates or inverters provide the complement of inputs.Ī common enable line is connected to each AND gate such that when EN= 0 all the outputs are zero and if EN=1, depends on the inputs A and B, outputs are produced. Thus, the logic circuit design of the 2-to-4 line decoder is given below which is implemented by using NOT and AND gates. These expressions can be implemented by using basic logic gates. ![]() This relationship between the inputs and outputs are illustrated in below truth table clearly.įrom the above truth table we can obtain Boolean expression for the each output as If the enable bit is zero then all the outputs will be set to zero. When both the inputs are high, then the output Y3 will be high. When A = 0 and B = 1, the output Y1 will be active and when A = 1 and B = 0, then the output Y2 will be active. When both inputs A and B are low (or A= B= 0), the output Y0 will be active or High and all other outputs will be low. For a given input, the outputs Y0 through Y3 are active high if enable input EN is active high (EN = 1). The figure below shows the truth table for a 2-to-4 decoder. Only one output is active at any time while the other outputs are maintained at logic 0 and the output which is held active or high is determined the two binary inputs A and B. In a 2-to-4 binary decoder, two inputs are decoded into four outputs hence it consists of two input lines and 4 output lines. The most commonly used practical binary decoders are 2-to-4 decoder, 3-to-8 decoder and 4-to-16 line binary decoder. ![]() Usually the number of bits in output code is more than the bits in its input code. Upon the availability of 2n lines, it activates the one of its output by deactivating (making logic 0) all other input whenever it receives n inputs. As an example, in case of BCD code, the 4 bit combinations from 0000 through 1001 are enough to represent the decimal digits 0 to 9.ĭepending on the number of input lines, the inputs of a binary code can be 2-bit or 3-bit or 4-bit codes. Generally, decoders are provided with enable inputs so as to activate the decoded output based on data inputs. ![]() The figure below shows the general structure of binary decoder in which encoded information is accepted at n input lines and the output is produced at 2n possible output lines. These are used when there is need to activate exactly one of 2n output based on an n-bit input value. A binary decoder is a multi-input, multi-output combinational circuit that converts a binary code of n input lines into a one out of 2n output code.
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